Current-sensing and repeater hybrid circuit technique for on-chip interconnects

Authors:
Atul Maheshwari;Wayne Burleson
Affiliations:
Logic Technology Development Group, Intel Corporation, Hillsboro, OR;Electrical and Computer Engineering Department, University of Massachusetts, Amherst, MA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2007

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Abstract

In this paper, hybrids based on current-sensing and repeaters are proposed for on-chip interconnects in an effort to overcome the limitations of these techniques. A novel receiver for current-sensing results in static power savings and allows an easier transition from current-sensing to traditional full rail voltage signals. Measurements of hybrids on a 0.18-µm CMOS technology show significant gains over repeater insertion in delay across wire lengths. Hybrids can also be used in placement constrained and low-noise scenarios to achieve delay and power benefits.