Methodology for energy-efficient digital circuit sizing: important issues and design limitations

Authors:
Bart R. Zeydel;Vojin G. Oklobdzija
Affiliations:
Advanced Computer Systems Engineering Laboratory, University of California, Davis, Davis, CA;Advanced Computer Systems Engineering Laboratory, University of California, Davis, Davis, CA
Venue:
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2006

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Abstract

This paper analyzes the issues that face digital circuit design methodologies and tools which address energy-efficient digital circuit sizing. The best known techniques for resolving these issues are presented, along with the sources of error. The analysis demonstrates that input slope independent models for energy and delay and stage based optimization are effective for analyzing and optimizing energy-efficient digital circuits when applied correctly.