Communications of the ACM
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Digital systems engineering
Practical Design of Globally-Asynchronous Locally-Synchronous Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications
Proceedings of the conference on Design, automation and test in Europe
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
Modelling and refinement of an on-chip communication architecture
ICFEM'05 Proceedings of the 7th international conference on Formal Methods and Software Engineering
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This paper discusses design of a modular self-timed communication platform aimed for high-performance globally asynchronous locally synchronous system-on-chip applications. The platform is based on a concurrent multitopology bus architecture with pipelined locally controlled transfer stages. Behavioral specification, handshake timing analysis technique and asynchronous circuit solutions for transfer stages are presented. Synchronization problems in component and bus communication are solved using self-timed approach. Deadlock prevention is implemented in logic level as a local autonomous function within each transfer stage. Different topologies and their building blocks are analyzed in terms of throughput, latency and implementation cost. According to simulations using a 0.18 µm technology, the overall maximum performance varied between 4.9 and 6.6 Gword/s depending on communication pattern and the bus topology.