Modelling and refinement of an on-chip communication architecture

Authors:
Juha Plosila;Pasi Liljeberg;Jouni Isoaho
Affiliations:
Dept. of Information Technology, University of Turku, Finland;Dept. of Information Technology, University of Turku, Finland;Dept. of Information Technology, University of Turku, Finland
Venue:
ICFEM'05 Proceedings of the 7th international conference on Formal Methods and Software Engineering
Year:
2005

Citing 4
Cited 1

Digital systems engineering

Digital systems engineering
A Discipline of Programming

A Discipline of Programming
Refinement Calculus: A Systematic Introduction

Refinement Calculus: A Systematic Introduction
Self-timed communication platform for implementing high-performance systems-on-chip

Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics

Time aware modelling and analysis of multiclocked VLSI systems

ICFEM'06 Proceedings of the 8th international conference on Formal Methods and Software Engineering

Quantified Score

Hi-index	0.01

Visualization

Abstract

In this paper, we present a formal modeling and refinement approach for on-chip communication architecture development, based on the Action Systems formalism. Stepwise refinement from an abstract high-level initial model to an implementable parallel switch based model is discussed. The focus is on gradually decomposing the initial specification into a composition of concurrently operating subsystems. Data transactions are modelled with atomic message passing events via interface procedures, for which a new notation is introduced. The concept is demonstrated by a network-like pipelined bus platform.