A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs

  • Authors:

  • Parag K. Lala;A. Singh;Alvernon Walker

  • Affiliations:

  • -;-;-

  • Venue:
  • DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
  • Year:
  • 1999

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Abstract

This paper proposes a logic cell that can be used as a building block for on-line testable FPGAs. The proposed logic cell consists of two 2-to-1 multiplexers, three 4-to-1 multiplexers and a D flip-flop. The cell has been designed using Differential Cascode Voltage Switch Logic. It is self-checking for all single transistor stuck-on and stuck-off faults as well as stuck-at faults at the inputs of each multiplexer and the D flip-flop. The multiplexers and the D flip-flop provide either correct (complementary) output in the absence of above-mentioned faults or identical outputs in the presence of fault.