Logic design principles with emphasis on testable semicustom circuits
Logic design principles with emphasis on testable semicustom circuits
Field-programmable gate arrays
Field-programmable gate arrays
Testing of uncustomized segmented channel field programmable gate arrays
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Efficiently supporting fault-tolerance in FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Novel technique for testing FPGAs
Proceedings of the conference on Design, automation and test in Europe
Tunable Fault Tolerance for Runtime Reconfigurable Architectures
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Defect tolerance at the end of the roadmap
Nano, quantum and molecular computing
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This paper presents a practical and low cost design-for-testability (DFT) scheme for the row-based field programmable gate array (FPGA) which is widely used for rapid prototyping, hardware verification/emulation of VLSI chips and manufacturing of complex digital systems. A new module is introduced for the DFT of the FPGA. The proposed DFT scheme permits the uncommitted FPGA to be tested using a set of constant cardinality (C-testability) for single and multiple stuck-at fault detection, while reducing the number of required primary test pins to only one. The number of tests for the FPGA is still 8+n/sub f/ (where n/sub f/ is the number of sequential modules in a row of the array), but only one primary pin and a small amount of testing circuitry are now required. This paper also modifies the single fault test set to accomplish multiple fault detection under two multiple fault models: the multiple fault single module (MFSM) and the single fault multiple module (SFMM) models. It is shown that by appropriately changing the don't care entries in the vectors of the test set for single fault detection, 100% and nearly 100% fault coverages can be achieved under the MFSM and SFMM models respectively.