A memory coherence technique for online transient error recovery of FPGA configurations
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
A formal approach to context scheduling for multicontext reconfigurable architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs
VLSI '99 Proceedings of the IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration: Systems on a Chip
DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
A Complete Data Scheduler for Multi-Context Reconfigurable Architectures
Proceedings of the conference on Design, automation and test in Europe
Run-Time Management of Logic Resources on Reconfigurable Systems
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Improving utilization of reconfigurable resources using two dimensional compaction
Proceedings of the conference on Design, automation and test in Europe
Improving utilization of reconfigurable resources using two-dimensional compaction
The Journal of Supercomputing
Real-Time Management of Hardware and Software Tasks for FPGA-based Embedded Systems
IEEE Transactions on Computers
Reliability and availability in reconfigurable computing: a basis for a common solution
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Dynamically reconfigurable systems have benefited from a new class of FPGAs recently introduced into the market, which allow partial and dynamic reconfiguration at run-time, enabling multiple independent functions from different applications to share the same device, swapping resources as needed. When the sequence of tasks to be performed is not predictable, resource allocation decisions have to be made on-line, fragmenting the FPGA logic space. A rearrangement may be necessary to get enough contiguous space to efficiently implement incoming functions, to avoid spreading their components and, as a result, degrading their performance. This paper presents a novel active replication mechanism for configurable logic blocks (CLBs), able to implement on-line rearrangements, defragmenting the available FPGA resources without disturbing those functions that are currently running.