Fast Template Placement for Reconfigurable Computing Systems
IEEE Design & Test
On-line Defragmentation for Run-Time Partially Reconfigurable FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Configuration Relocation and Defragmentation for Reconfigurable Computing
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
An efficient algorithm for finding empty space for online FPGA placement
Proceedings of the 41st annual Design Automation Conference
A Combinatorial Characterization of Higher-Dimensional Orthogonal Packing
Mathematics of Operations Research
Run-Time Management of Logic Resources on Reconfigurable Systems
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
New three-level resource management enhancing quality of offline hardware task placement on FPGA
International Journal of Reconfigurable Computing
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Partial reconfiguration allows parts of the reconfigurable chip area to be configured without affecting the rest of the chip. This allows placement of tasks at run time on the reconfigurable chip. Area management is a very important issue which highly affect the utilization of the chip and hence the performance. This paper focuses on a major aspect of moving running tasks to free space for new incoming tasks (compaction). We study the effect of compacting running tasks to free more contiguous space on the system performance. First, we introduce a straightforward compaction strategy called Blind compaction. We use its performance as a reference to measure the performance of other compaction algorithms. Then we propose a two-dimensional compaction algorithm called one-corner compaction. This algorithm runs with respect to one chip corner. We further extend this algorithm to the four corners of the chip and introduce the 4-corner compaction algorithm. Finally, we compare the performance of these algorithms with some existing compaction strategies [3]. The simulation results show improvement in average task allocation time when using the 4-corner compaction algorithm by 15% and in chip utilization by 16% over the Blind compaction. These results outperform the existing strategies.