A memory coherence technique for online transient error recovery of FPGA configurations
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Reconfigurable Architecture for Autonomous Self-Repair
IEEE Design & Test
A survey of fault tolerant methodologies for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Online fault tolerance for FPGA logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The inherent redundancy and in-the-field reconfiguration capabilities of field programmable gate arrays (FPGAs) provide alternatives to integrated circuit redundancy-based fault recovery techniques. An algorithm for efficient runtime recovery from permanent logic faults in the Xilinx 4000 architecture has been expanded to include interconnect fault recovery and has been applied to a diverse set of FPGA architectures. The post-fault-detection system downtime is minimized, and the end user need not have access to computer-aided design (CAD) tools, making the algorithm completely transparent to system users. Although some architectural features allow for a more efficient implementation, high levels of fault recovery with low timing and resource overhead can be achieved on these diverse architectures.