A fast algorithm for computing multiplicative inverses in GF(2m) using normal bases
Information and Computation
Low-Energy Digit-Serial/Parallel Finite Field Multipliers
Journal of VLSI Signal Processing Systems - Special issue on application specific systems, architectures and processors
Bit-Parallel Finite Field Multiplier and Squarer Using Polynomial Basis
IEEE Transactions on Computers
Reconfigurable Implementation of Elliptic Curve Crypto Algorithms
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Fully Parameterizable Elliptic Curve Cryptography Processor over GF(2)
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Fast Multiplication on Elliptic Curves over GF(2m) without Precomputation
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
A Reconfigurable System on Chip Implementation for Elliptic Curve Cryptography over GF(2n)
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
A Scalable Dual-Field Elliptic Curve Cryptographic Processor
IEEE Transactions on Computers
FPGA Implementation of a Microcoded Elliptic Curve Cryptographic Processor
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
A High Performance VLIW Processor for Finite Field Arithmetic
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Rapid Prototyping for Hardware Accelerated Elliptic Curve Public-Key Cryptosystems
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
High Performance FPGA based Elliptic Curve Cryptographic Co-Processor
ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
A microcoded elliptic curve processor using FPGA technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A high performance finite field processor for elliptic curve cryptography is presented. One of the contributions in this work is the modified Bit-Parallel Word-Serial (BPWS) finite field multiplication algorithm and its corresponding pipeline-fashion multiplier architecture. The proposed multiplier achieves a throughput of one multiplication every N + 1 clock cycles, in contrast with at least N + 3 clock cycles required in the recent other designs, where N is the ratio of field size to word size. Another contribution of this work is to explore parallelism at the instruction level in the proposed processor. Separated hardware modules for finite field multiplication, squaring and addition makes it possible that up to three finite field arithmetic operations be executed in parallel. At a higher level, data dependencies are detected at compile-time by analysing the data interdependency when performing elliptic curve point operations. Implemented using a CMOS 0.18 μm chip, which runs at 125MHz and performs one scalar multiplication in 62 μs.