Reconfigurable Elliptic Curve Cryptosystems on a Chip
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
High-speed hardware implementations of Elliptic Curve Cryptography: A survey
Journal of Systems Architecture: the EUROMICRO Journal
Journal of VLSI Signal Processing Systems
Hardware organization to achieve high-speed elliptic curve cryptography for mobile devices
Mobile Networks and Applications
On parallelization of high-speed processors for elliptic curve cryptography
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An FPGA based co-processor for elliptic curve cryptography
AsiaCSN '08 Proceedings of the Fifth IASTED International Conference on Communication Systems and Networks
Efficient finite field processor for GF(2163) and its implementation
International Journal of High Performance Systems Architecture
SPA resistant elliptic curve cryptosystem using addition chains
International Journal of High Performance Systems Architecture
Efficient time-area scalable ECC processor using µ-coding technique
WAIFI'10 Proceedings of the Third international conference on Arithmetic of finite fields
A high-performance unified-field reconfigurable cryptographic processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Customizable elliptic curve cryptosystems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An area-efficient universal cryptography processor for smart cards
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA implementation of point multiplication on koblitz curves using kleinian integers
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
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The implementation of a microcoded elliptic curve processor using field-programmable gate array technology is described. This processor implements optimal normal basis field operations in F(2/sup n/). The design is synthesized by a parameterized module generator, which can accommodate arbitrary n and also produce field multipliers with different speed/area tradeoffs. The control part of the processor is microcoded, enabling curve operations to be incorporated into the processor and hence reducing the chip's I/O requirements. The microcoded approach also facilitates rapid development and algorithmic optimization: for example, projective and affine coordinates were supported using different microcode. The design was successfully tested on a Xilinx Virtex XCV1000-6 device and could perform an elliptic curve multiplication over the field F(2/sup n/) using affine and projective coordinates for n=113,155, and 173.