Hardware Implementation of Montgomery's Modular Multiplication Algorithm
IEEE Transactions on Computers
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Elliptic curves in cryptography
Elliptic curves in cryptography
Handbook of Applied Cryptography
Handbook of Applied Cryptography
A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms
IEEE Transactions on Computers
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CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
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CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
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ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
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FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
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ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Fast exponentiation with precomputation
EUROCRYPT'92 Proceedings of the 11th annual international conference on Theory and application of cryptographic techniques
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CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
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ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Prime field ECDSA signature processing for reconfigurable embedded systems
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fast RSA implementation on itanium 2 processor
ICICS'06 Proceedings of the 8th international conference on Information and Communications Security
International Journal of Information and Computer Security
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This work proposes a new elliptic curve processor architecture for the computation of point multiplication for curves defined over fields GF(p). This is a scalable architecture in terms of area and speed specially suited for memory-rich hardware platforms such a field programmable gate arrays (FPGAs). This processor uses a new type of high-radix Montgomery multiplier that relies on the precomputation of frequently used values and on the use of multiple processing engines.