Real-time Euclid: a language for reliable real-time systems
IEEE Transactions on Software Engineering - Special issue on reliability and safety in real-time process control
Scheduling algorithms for hard real-time systems: a brief survey
Tutorial: hard real-time systems
Calculating the maximum, execution time of real-time programs
Real-Time Systems
Project Oberon: the design of an operating system and compiler
Project Oberon: the design of an operating system and compiler
Predicting program execution times by analyzing static and dynamic program paths
Real-Time Systems - Special issue: Real-time languages and language-level timing tools and analysis
Pipelined processors and worst case execution times
Real-Time Systems
ProfileMe: hardware support for instruction-level profiling on out-of-order processors
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Understanding some simple processor-performance limits
IBM Journal of Research and Development - Special issue: performance analysis and its impact on design
A programmer's view of performance monitoring in the PowerPC microprocessor
IBM Journal of Research and Development - Special issue: performance analysis and its impact on design
Advanced compiler design and implementation
Advanced compiler design and implementation
Bounding Pipeline and Instruction Cache Performance
IEEE Transactions on Computers
Complete worst-case execution time analysis of straight-line hard real-time programs
Journal of Systems Architecture: the EUROMICRO Journal - Special issue on real-time systems
An Accurate Worst Case Timing Analysis for RISC Processors
IEEE Transactions on Software Engineering
Efficient worst case timing analysis of data caching
RTAS '96 Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium (RTAS '96)
Supporting the specification and analysis of timing constraints
RTAS '96 Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium (RTAS '96)
Adding instruction cache effect to schedulability analysis of preemptive real-time systems
RTAS '96 Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium (RTAS '96)
OS-Controlled Cache Predictability for Real-Time Systems
RTAS '97 Proceedings of the 3rd IEEE Real-Time Technology and Applications Symposium (RTAS '97)
Efficient Run-Time Monitoring of Timing Constraints
RTAS '97 Proceedings of the 3rd IEEE Real-Time Technology and Applications Symposium (RTAS '97)
Bounding Loop Iterations for Timing Analysis
RTAS '98 Proceedings of the Fourth IEEE Real-Time Technology and Applications Symposium
Tighter Timing Predictions by Automatic Detection and Exploitation of Value-Dependent Constraints
RTAS '99 Proceedings of the Fifth IEEE Real-Time Technology and Applications Symposium
Analysis of cache-related preemption delay in fixed-priority preemptive scheduling
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Cache modeling for real-time software: beyond direct mapped instruction caches
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Combining Abstract Interpretation and ILP for Microarchitecture Modelling and Program Path Analysis
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
Testing the Results of Static Worst-Case Execution-Time Analysis
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
A Worst Case Timing Analysis Technique for Multiple-Issue Machines
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
Relative roles of instruction count and cycles per instruction in WCET estimation
Proceedings of the 2nd ACM/SPEC International Conference on Performance engineering
Estimation of probabilistic bounds on phase CPI and relevance in WCET analysis
Proceedings of the tenth ACM international conference on Embedded software
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The control system of many complex mechatronic products requires for each task the Worst Case Execution Time (WCET), which is needed for the scheduler's admission tests and subsequently limits a task's execution time during operation. If a task exceeds the WCET, this situation is detected and either a handler is invoked or control is transferred to a human operator. Such control systems usually support preemptive multitasking, and if an object-oriented programming language (e.g., Java, C++, Oberon) is used, then the system may also provide dynamic loading and unloading of software components (modules). Only modern, state-of-the art microprocessors can provide the necessary compute cycles, but this combination of features (preemption, dynamic un/loading of modules, advanced processors) creates unique challenges when estimating the WCET. Preemption makes it difficult to take the state of the caches and pipelines into account when determining the WCET, yet for modern processors, a WCET based on worst-case assumptions about caches and pipelines is too large to be useful, especially for big and complex real-time products. Since modules can be loaded and unloaded, each task must be analyzed in isolation, without explicit reference to other tasks that may execute concurrently. To obtain a realistic estimate of a task's execution time, we use static analysis of the source code combined with information about the task's runtime behavior. Runtime information is gathered by the performance monitor that is included in the processor's hardware implementation. Our predictor is able to compute a good estimation of the WCET even for complex tasks that contain a lot of dynamic cache usage, and its requirements are met by today's performance monitoring hardware. The paper includes data to evaluate the effectiveness of the proposed technique for a number of robotics control kernels that are written in an object-oriented programming language and execute on a PowerPC 604e-based system.