Thumb: Reducing the Cost of 32-bit RISC Performance in Portable and Consumer Applications

Authors:
Liam Goudge;Simon Segars
Affiliations:
-;-
Venue:
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
Year:
1996

Citing 5
Cited 15

Computer architecture: a quantitative approach

Computer architecture: a quantitative approach
Incredible shrinking computers

IEEE Spectrum
VLSI RISC Architecture and Organization

VLSI RISC Architecture and Organization
The Test Access Port and Boundary-Scan Architecture

The Test Access Port and Boundary-Scan Architecture
The Challenges of Mobile Computing

Computer

An extended addressing mode for low power

ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Code-Size Minimization in Multiprocessor Real-Time Systems

IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 2 - Volume 03
A software-only compression system for trading-offs between performance and code size

SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
Instruction set synthesis with efficient instruction encoding for configurable processors

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Selective code transformation for dual instruction set processors

ACM Transactions on Embedded Computing Systems (TECS) - SPECIAL ISSUE SCOPES 2005
Efficient code size reduction without performance loss

Proceedings of the 2007 ACM symposium on Applied computing
ASIP instruction encoding for energy and area reduction

Proceedings of the 44th annual Design Automation Conference
The QC-2 parallel Queue processor architecture

Journal of Parallel and Distributed Computing
NISD: A Framework for Automatic Narrow Instruction Set Design

ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Efficient compilation for queue size constrained queue processors

Parallel Computing
Compiler Support for Code Size Reduction Using a Queue-Based Processor

Transactions on High-Performance Embedded Architectures and Compilers II
Compiling for Reduced Bit-Width Queue Processors

Journal of Signal Processing Systems
An efficient code generation algorithm for code size reduction using 1-offset P-code queue computation model

EUC'07 Proceedings of the 2007 international conference on Embedded and ubiquitous computing
Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture

The Journal of Supercomputing
A compositional framework for real-time embedded systems

ISAS'05 Proceedings of the Second international conference on Service Availability

Quantified Score

Hi-index	0.00

Visualization

Abstract

) This article discusses a RISC architectural innovation from ARM known as Thumb. High-end embedded control applications such as cell-phones, disk drives and modems are demanding more performance from their controllers while still requiring low cost. By implementing a second "compressed" instruction set, Thumb reduces RISC code size and so provides 32-bit ARM RISC performance and power consumption at 8/16-bit system cost.