An object code compression approach to embedded processors
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Selective instruction compression for memory energy reduction in embedded systems
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Code compression for low power embedded system design
Proceedings of the 37th Annual Design Automation Conference
Cached-code compression for energy minimization in embedded processors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Design of an one-cycle decompression hardware for performance increase in embedded systems
Proceedings of the 39th annual Design Automation Conference
An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs
Proceedings of the conference on Design, automation and test in Europe
Compilation framework for code size reduction using reduced bit-width ISAs (rISAs)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 41st annual Design Automation Conference
Selective code transformation for dual instruction set processors
ACM Transactions on Embedded Computing Systems (TECS) - SPECIAL ISSUE SCOPES 2005
From classroom to research: providing different services for computer architecture education
WCAE '07 Proceedings of the 2007 workshop on Computer architecture education
Reducing instruction bit-width for low-power VLIW architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Energy consumption is emerging as a critical design concern for programmable embedded systems. Many Reduced Bit-width Instruction Set Architectures (rISA) (e.g., ARM Thumb) are being increasingly used to decrease code size. Previous work has explored energy savings in non-cached rISA architectures as a byproduct of code size reduction. In this paper we present an energy efficient code generation technique for rISA architectures, and furthermore explore energy savings for both cached and non-cached architectures. Our code generation technique uses profile information to find the most frequently executed parts of the program. By aggressively reducing code size on frequently executed parts, fewer fetches to instruction memory are incurred, thus reducing the power consumption of the instruction memory. We achieve an average 30% reduction in instruction memory energy consumption in cached systems, on a variety of benchmarks, as compared to non-rISA architectures.