LISA—machine description language for cycle-accurate models of programmable DSP architectures
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Computer
Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA)
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
| Hi-index | 0.00 |
T&D-Bench (Teaching and Design Workbench) is now a mature framework for processor modeling and simulation. The framework's processor models have been employed by students to execute practical exercises in Computer Architecture (CA) courses and, by the instructors, to illustrate CA concepts in classroom. The framework itself has been employed by seniors and researchers to make the design space exploration of embedded processors, which is accomplished by modeling new processors or by extensions to the existing processor models. The results of the research activities, incorporated to the processor models, may then be employed in classroom, producing a virtuous circle. This work describes all the services developed for T&D-Bench along the last years. For example, a practical use in research to model an architectural feature that reduces energy consumption, as well as a comparison with a well-established Architecture Description Language are presented.