Microarchitecture and compiler techniques for dual width isa processors

• Authors: Rajiv Gupta;Arvind Krishnaswamy
• Venue: Microarchitecture and compiler techniques for dual width isa processors
• Year: 2006

Embedded processors have to execute programs under the constraints of limited resources such as memory and power. As a result, code size becomes as important a metric as performance when evaluating applications written for the embedded domain. Existing techniques improve one program metric at the cost of the other. Simultaneously achieving good code size and performance is a challenging problem. This dissertation proposes compiler and microarchitectural techniques that address this problem. Dual-Width ISA processors provide a platform with two instruction sets---a 32-bit instruction set yielding fast programs and a 16-bit instruction set yielding small programs. The techniques described here exploit properties of dual-width ISA processors to bridge the gap between the small programs and the fast programs by improving the performance of 16-bit programs, yielding small and fast programs. An integrated microarchitectural/compiler framework (Dynamic Instruction Coalescing) and a purely microarchitectural framework (Dynamic Eager Execution) are proposed. Dynamic Instruction Coalescing introduces a new kind of instruction---an Augmenting eXtension or AX. AX instructions are dynamically coalesced with the succeeding instruction at no cost. Efficient compiler techniques are proposed to use AX instructions to perform local and global optimizations that improve performance without negatively affecting code size. Dynamic Eager Execution is a microarchitecture that improves the performance of 16-bit programs by eagerly executing instructions. This framework comprises two techniques namely Dynamic Delayed Branching and Dynamic 2-wide Execution. The first improves branch behavior and the other seeks to improve program execution by simultaneously issuing multiple instructions.