The Design of a Register Renaming Unit

Authors:
Benjamin Bishop;Thomas P. Kelliher;Mary Jane Irwin
Affiliations:
-;-;-
Venue:
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Year:
1999

Citing 0
Cited 10

Wattch: a framework for architectural-level power analysis and optimizations

Proceedings of the 27th annual international symposium on Computer architecture
Energy reduction in queues and stacks by adaptive bitwidth compression

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator

PACS '00 Proceedings of the First International Workshop on Power-Aware Computer Systems-Revised Papers
High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core

The Journal of Supercomputing
On the latency, energy and area of checkpointed, superscalar register alias tables

ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
The QC-2 parallel Queue processor architecture

Journal of Parallel and Distributed Computing
Dual-execution mode processor architecture

The Journal of Supercomputing
On the latency and energy of checkpointed superscalar register alias tables

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dual-execution mode processor architecture for embedded applications

Journal of Mobile Multimedia
The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing

ACM Transactions on Architecture and Code Optimization (TACO)

Quantified Score

Hi-index	0.00

Visualization

Abstract

Register renaming is often used to improve performance in many high-ILP processors. However, there is a lack of publications regarding register renaming hardware design. This paper presents a detailed look at one possible implementation of a register renaming unit, as well as some possible optimizations.