Data driven signal processing: an approach for energy efficient computing
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Embedded power supply for low-power DSP
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Run-time voltage hopping for low-power real-time systems
Proceedings of the 37th Annual Design Automation Conference
A low power scheduling scheme with resources operating at multiple voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Managing power and performance for System-on-Chip designs using Voltage Islands
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Optimal procrastinating voltage scheduling for hard real-time systems
Proceedings of the 42nd annual Design Automation Conference
On multiple-voltage high-level synthesis using algorithmic transformations
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal simultaneous module and multivoltage assignment for low power
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimality study of resource binding with multi-Vdds
Proceedings of the 43rd annual Design Automation Conference
Distributed DVFS using rationally-related frequencies and discrete voltage levels
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
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The energy efficiency of a CMOS architecture processing dynamic workloads directly affects its ability to provide long battery lifetimes while maintaining required application performance. Existing scalable architecture design approaches are often limited in scope, focusing either only on circuit-level optimizations or architectural adaptations individually. In this paper, we propose a circuit/architecture co-design methodology called Panoptic Dynamic Voltage Scaling (PDVS) that makes more efficient use of common circuit structures and algorithm-level processing rate control. PDVS expands upon prior work by using multiple component-level PMOS header switches to enable fine-grained rate control, allowing efficient dithering among statically scheduled algorithms with sub-block energy savings. This way, PDVS is able to achieve a wide variety of processing rates to match incoming workload as closely as possible, while each iteration takes less energy to process than on architectures with coarser levels of rate control. Measurements taken from a fabricated 90nm test chip characterize both savings and overheads and are used to inform PDVS synthesis decisions. Results show that PDVS consumes up to 34% and 44% less energy than Multi-VDD and Single-VDD systems, respectively.