Analog VLSI and neural systems
Analog VLSI and neural systems
Transistor sizing issues and tool for multi-threshold CMOS technology
DAC '97 Proceedings of the 34th annual Design Automation Conference
Embedded power supply for low-power DSP
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Design methodology for fine-grained leakage control in MTCMOS
Proceedings of the 2003 international symposium on Low power electronics and design
Level conversion for dual-supply systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sub-threshold Design for Ultra Low-Power Systems (Series on Integrated Circuits and Systems)
Sub-threshold Design for Ultra Low-Power Systems (Series on Integrated Circuits and Systems)
Analysis and optimization of sleep modes in subthreshold circuit design
Proceedings of the 44th annual Design Automation Conference
A subthreshold to above-threshold level shifter comprising a Wilson current mirror
IEEE Transactions on Circuits and Systems II: Express Briefs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper we present low power level shifters in the 90nm (general purpose) and 65nm (low power) technology nodes capable of converting subthreshold voltage signals to above threshold voltage signals. The level shifters make use of the MTCMOS design technique which gives more design flexibility, especially in low power systems. Post layout simulations indicate static power consumption down to 1nW and 83pW in the 90nm and 65nm process respectively. Energy consumption per transition is recorded to be below 30fJ in both processes, orders of magnitude lower then other published level shifter implementations. Propagation delay is found to be as low as 32ns for subthreshold logic high input signals of 180mV. The functionality of the level shifters is verified across process-, mismatch- and temperature variations between -40^oC and 150^oC. Minimum input voltage attainable while maintaining robust operation is found to be around 180mV at operational frequencies above 1MHz in the 90nm process, and 350mV at operational frequencies above 500kHz in the 65nm process. The level shifters employ an enable/disable feature, allowing for power saving when the level shifter is not in use.