Cache coherence protocols: evaluation using a multiprocessor simulation model
ACM Transactions on Computer Systems (TOCS)
Hierarchical cache/bus architecture for shared memory multiprocessors
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
An evaluation of directory schemes for cache coherence
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Analysis and Comparison of Cache Coherence Protocols for a Packet-Switched Multiprocessor
IEEE Transactions on Computers
SIGMETRICS '86/PERFORMANCE '86 Proceedings of the 1986 ACM SIGMETRICS joint international conference on Computer performance modelling, measurement and evaluation
Implementing a cache consistency protocol
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Performance '87 Proceedings of the 12th IFIP WG 7.3 International Symposium on Computer Performance Modelling, Measurement and Evaluation
Using cache memory to reduce processor-memory traffic
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
A low-overhead coherence solution for multiprocessors with private cache memories
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
An economical solution to the cache coherence problem
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Theory, Volume 1, Queueing Systems
Theory, Volume 1, Queueing Systems
Mapping applications onto a cache coherent multiprocessor
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
Design and Analysis of Cache Coherent Multistage Interconnection Networks
IEEE Transactions on Computers
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Designing efficient cache coherence schemes for shared memory multiprocessors has attracted much attention of the researchers in the area. Snoopy cache protocols have been designed for bus based multiprocessors. However, the snoopy protocols are not applicable to general interconnection networks. On the other hand, the directory based cache protocols adapt very well to any kind of interconnection network such as a Multistage Network. Since different protocols have different cost overheads, and may give different performance, the protocol to be used must be wisely selected. Although there has been some simulation studies on the behavior of different directory schemes proposed in the literature, there has been no systematic analytical model for these schemes. In this paper we develop a detailed analytical model of the various directory schemes on a Multistage Interconnection Network. The shared miss ratios are computed analytically, and the performance of the various schemes is compared. Results are presented to show that the directories do not form a system bottleneck contrary to popular belief.