Impact of Switch Design on the Application Performance of Cache-Coherent Multiprocessors

• Venue: IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
• Year: 1998

In this paper, the effect of switch design on the application peformance of cache-coherent non-uniform memory access (CC-NUMA) multiprocessors is studied in detail. Wormhole routing and cut-through switching are evaluated for these shared-memory multiprocessors that employ multistage interconnection network (MIN) and full map directory-based cache coherence protocol. The switch design also considers virtual channels and varying number of input buffers per switch. Based on this, four different switch architectures are presented and compared. The evaluation is based on execution-driven simulation using five different applications to capture the random bursty nature of the network trafic arrival. The round-robin memory management policy is implemented. We show that the use of cut-through switching with buffers and virtual channels improves the average message latency tremendously. The waiting times of messages at various stages of switches are also presented. Finally, we show the variation of stall times and execution times for these applications by varying the switch delay and wire width.