Dynamically-Allocated Multi-Queue Buffers for VLSI Communication Switches
IEEE Transactions on Computers
Gigabit networking
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IEEE/ACM Transactions on Networking (TON)
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SIGCOMM '95 Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
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Proceedings of the 29th conference on Winter simulation
Efficient Broadcast and Multicast on Multistage Interconnection Networks Using Multiport Encoding
IEEE Transactions on Parallel and Distributed Systems
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Tiny Tera: A Packet Switch Core
IEEE Micro
Spider: A High-Speed Network Interconnect
IEEE Micro
Symmetric Crossbar Arbiters for VLSI Communication Switches
IEEE Transactions on Parallel and Distributed Systems
PCRCW '94 Proceedings of the First International Workshop on Parallel Computer Routing and Communication
The Monsoon Interconnection Network
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
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COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
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IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
HIPIQS: A High-Performance Switch Architecture using Input Queuing
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
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IEEE Transactions on Parallel and Distributed Systems
Evaluating kilo-instruction multiprocessors
WMPI '04 Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture
FIFO-Based Multicast Scheduling Algorithm for Virtual Output Queued Packet Switches
IEEE Transactions on Computers
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IEEE/ACM Transactions on Networking (TON)
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Proceedings of the 21st annual symposium on Integrated circuits and system design
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Proceedings of the 2009 International Conference on Computer-Aided Design
HiPC'05 Proceedings of the 12th international conference on High Performance Computing
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Switch-based interconnects are used in a number of application domains, including parallel system interconnects, local area networks, and wide area networks. However, very few switches have been designed that are suitable for more than one of these application domains. Such a switch must offer both extremely low latency and very high throughput for a variety of different message sizes. While some architectures with output queuing have been shown to perform extremely well in terms of throughput, their performance can suffer when used in systems where a significant portion of the packets are extremely small. On the other hand, architectures with input queuing offer limited throughput or require fairly complex and centralized arbitration that increases latency. In this paper, we present a new input queue-based switch architecture called HIPIQS (HIgh-Performance Input-Queued Switch). It offers low latency for a range of message sizes and provides throughput comparable to that of output queuing approaches. Furthermore, it allows simple and distributed arbitration. HIPIQS uses a dynamically allocated multiqueue organization, pipelined access to multibank input buffers, and small cross-point buffers to deliver high performance. Our simulation results show that HIPIQS can deliver performance close to that of output queuing approaches over a range of message sizes, system sizes, and traffic. The switch architecture can therefore be used to build high performance switches that are useful for both parallel system interconnects and for building computer networks.