An introduction to parallel algorithms
An introduction to parallel algorithms
The iSLIP scheduling algorithm for input-queued switches
IEEE/ACM Transactions on Networking (TON)
HIPIQS: A High-Performance Switch Architecture Using Input Queuing
IEEE Transactions on Parallel and Distributed Systems
Approaches to optical Internet packet switching
IEEE Communications Magazine
Optical routing of asynchronous, variable length packets
IEEE Journal on Selected Areas in Communications
Exploitation of DWDM for optical packet switching with quality of service guarantees
IEEE Journal on Selected Areas in Communications
IEEE Journal on Selected Areas in Communications
An enhanced OPS architecture with optical buffers
HONET'09 Proceedings of the 6th international conference on High capacity optical networks and enabling technologies
Performance analysis of a packet prioritisation algorithm for optical-packet-switching networks
International Journal of Ad Hoc and Ubiquitous Computing
A latency-aware scheduling algorithm for all-optical packet switching networks with FDL buffers
Photonic Network Communications
Photonic Network Communications
Pipelining multicast scheduling in all-optical packet switches with delay guarantee
Proceedings of the 23rd International Teletraffic Congress
An analytical model for all-optical packet switching networks with finite FDL buffers
Photonic Network Communications
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We develop a method of high-speed buffer management for output-buffered photonic packet switches. The use of optical fiber delay lines is a promising solution to constructing optical buffers. The buffer manager determines packet delays in the fiber delay line buffer before the packets arrive at the buffer. We propose a buffer management method based on a parallel and pipeline processing architecture consisting of (log2 N + 1) pipeline stages, where N is the number of ports of the packet switch. This is an expansion of a simple sequential scheduling used to determine the delays of arriving packets. Since the time complexity of each processor in the pipeline stages is O(1), the throughput of this buffer management is N times larger than that of the sequential scheduling method. This method can be used for buffer management of asynchronously arriving variable-length packets. We show the feasibility of a buffer manager supporting 128 × 40 Gb/s photonic packet switches, which provide at least eight times as much throughput as the latest electronic IP routers. The proposed method for asynchronous packets overestimates the buffer occupancy to enable parallel processing. We show through simulation experiments that the degradation in the performance of the method resulting from this overestimation is quite acceptable.