On the design of asynchronous optical packet switch architectures with shared delay lines and converters

  • Authors:
  • Haitham S. Hamza;Tawfik Ismail;Khaled El-Sayed

  • Affiliations:
  • Department of Information Technology, Faculty of Computes and Information, Cairo University, Giza, Egypt 12613;Department of Information Technology, Faculty of Computes and Information, Cairo University, Giza, Egypt 12613;Department of Information Technology, Faculty of Computes and Information, Cairo University, Giza, Egypt 12613

  • Venue:
  • Photonic Network Communications
  • Year:
  • 2011

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Abstract

Optical packet switching (OPS) is a promising technology to enable next-generation high-speed IP networks. A major issue in OPS is packet contention that occurs when two or more packets attempt to access the same output fiber. In such a case, packets may be dropped, leading to degraded overall switching performance. Several contention resolution techniques have been investigated in the literature including the use of fiber delay lines (FDLs), wavelength converters (WCs), and deflection routing. These solution typically induce extra complexity to the switch design. Accordingly, a key design objective for OPS is to reduce packet loss without increasing switching complexity and delay. In this paper, we investigate the performance of contention resolution in asynchronous OPS architectures with shared FDLs and WCs in terms of packet loss and average switching delay. In particular, an enhanced FDL-based and a novel Hybrid architecture with shared FLDs and WCs are proposed, and their packet scheduling algorithms are presented and evaluated. Extensive simulation studies show that the performance of proposed FDL-based architecture outperforms typical OPS architectures reported in the literature. In addition, it shown that, for the same packet loss ratio, the proposed hybrid architecture can achieve up to 30% reduction in the total number of ports and around 80% reduction in the overall length of fiber as compared to the FDL-based architectures.