Tempest and typhoon: user-level shared memory
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
The performance impact of flexibility in the Stanford FLASH multiprocessor
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
The MIT Alewife machine: architecture and performance
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
STiNG: a CC-NUMA computer system for the commercial marketplace
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
The directory-based cache coherence protocol for the DASH multiprocessor
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
IEEE Micro
The DASH Prototype: Logic Overhead and Performance
IEEE Transactions on Parallel and Distributed Systems
System Overview of the SGI Origin 200/2OOO Product Line
COMPCON '97 Proceedings of the 42nd IEEE International Computer Conference
Origin System Design Methodology and Experience: lM-gate ASICs and Beyond
COMPCON '97 Proceedings of the 42nd IEEE International Computer Conference
The SGI Origin Software Environment and Application Performance
COMPCON '97 Proceedings of the 42nd IEEE International Computer Conference
The evolution of the HP/Convex Exemplar
COMPCON '97 Proceedings of the 42nd IEEE International Computer Conference
A New Solution to Coherence Problems in Multicache Systems
IEEE Transactions on Computers
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Achieving scalability in computer systems without sacrificing usability, requires a synergistic combination of system architecture, fundamental technologies, and implementation. This paper discusses how the Silicon Graphics Origin system utilizes these elements to create a truly scalable microprocessor and makes predictions of how these elements will evolve to provide performance growth into the next century. The paper begins by reviewing current multiprocessor alternatives, and producing the notion of a scalable SMP. The second part of the paper focuses on a particular instance of a scalable SMP, the Silicon Graphics Origin multiprocessor and its S/sup 2/MP memory architecture. We give an overview of the Origin system architecture and then discuss some of the core technologies and key implementation components of the system. In the final section we examine how technology trends will impact system architecture and what key technologies and implementation strategies are implied by those trends. We go on to predict that clusters of scalable shared-memory multiprocessors will become the dominant, multiprocessor architecture.