The Formal Design of 1M-gate ASICs
Formal Methods in System Design - Special issue on formal methods for computer-added design
The Formal Design of 1M-gate ASICs
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Scalability in computing for today and tomorrow
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Server I/O networks past, present, and future
NICELI '03 Proceedings of the ACM SIGCOMM workshop on Network-I/O convergence: experience, lessons, implications
Using Hardware Counters to Automatically Improve Memory Performance
Proceedings of the 2004 ACM/IEEE conference on Supercomputing
Hamiltonian cycle within extended OTIS-cube topology
ACELAE'11 Proceedings of the 10th WSEAS international conference on communications, electrical & computer engineering, and 9th WSEAS international conference on Applied electromagnetics, wireless and optical communications
Topological properties of the Extended OTIS-n-Cube interconnection network
The Journal of Supercomputing
k-pairwise disjoint paths routing in perfect hierarchical hypercubes
The Journal of Supercomputing
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The SGI Origin 200/2000 is a cache-coherent non-uniform memory access (ccNUMA) multiprocessor, designed and manufactured by Silicon Graphics Inc. (SGI). The Origin system was designed from the ground up as a multiprocessor that was capable of scaling to both small and large processor counts without any cost, bandwidth or latency cliffs. The Origin system consists of up to 512 nodes interconnected by a highly scalable Craylink network. Each node consists of one or two R10000 processors and up to 4 GBytes of coherent memory. Each node also connects to the scalable XIO I/O subsystem. This paper discusses the motivation for building the Origin 200/2000 and describes its architecture and implementation.