Cache coherence protocols: evaluation using a multiprocessor simulation model
ACM Transactions on Computer Systems (TOCS)
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ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
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ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
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ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Memory consistency and event ordering in scalable shared-memory multiprocessors
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
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MASCOTS '94 Proceedings of the Second International Workshop on Modeling, Analysis, and Simulation On Computer and Telecommunication Systems
How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
IEEE Transactions on Computers
A New Solution to Coherence Problems in Multicache Systems
IEEE Transactions on Computers
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Cache memories are widely accepted in shared-memory multiprocessor system because they make it possible to reduce network traffics and memory latencies. However, they impose substantial overheads of cache coherency maintenance and also engender some inefficiencies of coherence misses.This paper presents that constraints of cache coherency can be relaxed in a region where exclusive accesses are guaranteed by synchronization operations, so that the execution time of parallel programs can be decreased. When an acquire operation occurs, cache coherence protocol could not be applied to the operations following an acquire operation until a release operation is issued. The updated data in the region are transferred to other processors when a release operation is performed. We alleviate the overheads of release operations using QOLB synchronization primitives. By a program-driven simulation, our new cache coherence protocol shows performance improvement in most of parallel applications, and also execution times can be reduced effectively as the number of processors are increased.