An evaluation of directory schemes for cache coherence
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
False Sharing and Spatial Locality in Multiprocessor Caches
IEEE Transactions on Computers
MINT: A Front End for Efficient Simulation of Shared-Memory Multiprocessors
MASCOTS '94 Proceedings of the Second International Workshop on Modeling, Analysis, and Simulation On Computer and Telecommunication Systems
A New Solution to Coherence Problems in Multicache Systems
IEEE Transactions on Computers
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In multiprocessor systems, the cache misses due to coherence transactions make up many of the total cache misses. However this type of cache miss is strongly dependent on the type of data sharing among processors, especially false sharing. Until now the small cache block size has been used to avoid false sharing mainly in multiprocessor systems, but the smaller the cache block size, the lower the prefetching effect. Moreover it is shown that high spatial locality appears in many parallel programs. The paper presents two advanced full-map directory schemes which provide a low cache miss ratio and communication traffic by avoiding false sharing and taking advantage of the spatial locality existing in many parallel programs. The performance was evaluated by the event-driven simulator and the empirical results show that the proposed scheme can provide about a 6/spl sim/77% decrease in the cache miss ratio and a 46/spl sim/96% decrease in the communication traffic.