An Augmented Content-Addressed Memory Array for Implementation With Large-Scale Integration
Journal of the ACM (JACM)
Content Addressable Parallel Processors
Content Addressable Parallel Processors
Multiple-Response Resolution in Associative Systems
IEEE Transactions on Computers
Data Manipulating Functions in Parallel Processors and Their Implementations
IEEE Transactions on Computers
Determination of Priority in Associative Memories
IEEE Transactions on Computers
Cellular Logic-in-Memory Arrays
IEEE Transactions on Computers
A cryotron catalog memory system
AIEE-IRE '56 (Eastern) Papers and discussions presented at the December 10-12, 1956, eastern joint computer conference: New developments in computers
Associative memory with ordered retrieval
IBM Journal of Research and Development
Fast Search Algorithms for Associative Memories
IEEE Transactions on Computers
MANIP A Multicomputer Architecture for Solving Combinatonal Extremum-Search Problems
IEEE Transactions on Computers
The Analysis and Design of Some New Sorting Machines
IEEE Transactions on Computers
An Optimal Algorithm for Scheduling Requests on Interleaved Memories for a Pipelined Processor
IEEE Transactions on Computers
PUMPS Architecture for Pattern Analysis and Image Database Management
IEEE Transactions on Computers
The architecture of MANIP: a parallel computer system for solving NP-complete problems
AFIPS '81 Proceedings of the May 4-7, 1981, national computer conference
Highly parallel associative search and its application to cellular database machine design
AFIPS '81 Proceedings of the May 4-7, 1981, national computer conference
DIALOG: a distributed processor organization for database machine
AFIPS '80 Proceedings of the May 19-22, 1980, national computer conference
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In this paper, we design some simple schemes for a variety of searches, each of which may be performed in one complete memory cycle using bit-memory logic primarily. The searches we study include the basic equality search, the threshold searches (both greater than and less than searches), and most importantly, the greatest value and the least value searches. For each kind of search, we present both the algorithm suitable for our needs and the logic circuit of the memory cell required by the algorithm. Based on the basic search schemes, an algorithm for ordered retrieval is developed. A comparison for ordered retrieval schemes is then made between the proposed scheme and the previous algorithms. It is found that this algorithm outperforms all the other algorithms compared, particularly in the resolution of multiple responses. Finally, issues relating to LSI implementation, manufacturing defects, modular expansion, and extension to associative sequential memories are discussed.