Multimedia Information Retrieval: Content-Based Information Retrieval from Large Text and Audio Databases
The theory of parsing, translation, and compiling
The theory of parsing, translation, and compiling
PKDD '98 Proceedings of the Second European Symposium on Principles of Data Mining and Knowledge Discovery
VLSI architectures for high speed recognition of context-free languages and finite-state languages
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Accelerating the CKY Parsing Using FPGAs
HiPC '02 Proceedings of the 9th International Conference on High Performance Computing
An FPGA-Based Syntactic Parser for Real-Life Almost Unrestricted Context-Free Grammars
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
DESIGN OF A HIGH SPEED STRING MATCHING CO-PROCESSOR FOR NLP
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Reconfigurable content-based router using hardware-accelerated language parser
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient reconfigurable embedded parsers
Computer Languages, Systems and Structures
A Formal Method for Rapid SoC Prototyping
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
A platform for the automatic generation of attribute evaluation hardware systems
Computer Languages, Systems and Structures
A parallel BSP algorithm for irregular dynamic programming
APPT'07 Proceedings of the 7th international conference on Advanced parallel processing technologies
Fine-grained parallel RNA secondary structure prediction using SCFGs on FPGA
Parallel Computing
A tunable coarse-grained parallel algorithm for irregular dynamic programming applications
HiPC'04 Proceedings of the 11th international conference on High Performance Computing
Accelerating ncRNA homology search with FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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This paper presents an FPGA-based implementation of a co-processing unit able to parse context-free grammars of real-life sizes. The application fields of such a parser range from programming languages syntactic analysis to very demanding Natural Language Applications where parsing speed is an important issue.