Parallel parsing on a one-way array of finite-state machines
IEEE Transactions on Computers
Efficient parallel algorithms
Essence of generalized partial computation
Theoretical Computer Science - Images of programming dedicated to the memory of Andrei P. Ershov
Partial evaluation and automatic program generation
Partial evaluation and automatic program generation
Statistical Language Learning
Introduction to Languages and the Theory of Computation
Introduction to Languages and the Theory of Computation
The theory of parsing, translation, and compiling
The theory of parsing, translation, and compiling
An FPGA-Based Syntactic Parser for Real-Life Almost Unrestricted Context-Free Grammars
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
An FPGA-Based Coprocessor for the Parsing of Context-Free Grammars
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Efficient parallel CKY parsing on GPUs
IWPT '11 Proceedings of the 12th International Conference on Parsing Technologies
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The main contribution of this paper is to present an FPGA-based implementation of an instance-specific hardware which accelerates the CKY (Cook-Kasami-Younger) parsing for context-free grammars. Given a context-free grammar G and a string x, the CKY parsing determines if G derives x. We have developed a hardware generator that creates a Verilog HDL source to perform the CKY parsing for any given context-free grammar G. The created source is embedded in an FPGA using the design software provided by the FPGA vendor. We evaluated the instance-specific hardware, generated by our hardware generator, using a timing analyzer and tested it using the Altera FPGAs. The generated hardware attains a speed-up factor of approximately 750 over the software CKY parsing algorithm. Hence, we believe that our approach is a promising solution for the CKY parsing.