Syntactic Pattern Recognition of the ECG
IEEE Transactions on Pattern Analysis and Machine Intelligence
Parallel Recognition and Parsing on the Hypercube
IEEE Transactions on Computers
Eli: a complete, flexible compiler construction system
Communications of the ACM
Artificial intelligence: a modern approach
Artificial intelligence: a modern approach
Attribute grammar paradigms—a high-level methodology in language implementation
ACM Computing Surveys (CSUR)
A parallel parsing algorithm for arbitrary context-free grammars
Information Processing Letters
An Improved Context-Free Recognizer
ACM Transactions on Programming Languages and Systems (TOPLAS)
An efficient context-free parsing algorithm
Communications of the ACM
An FPGA-Based Coprocessor for the Parsing of Context-Free Grammars
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
An Embedded Microprocessor for Intelligent Control
Journal of Intelligent and Robotic Systems
Compilers: Principles, Techniques, and Tools (2nd Edition)
Compilers: Principles, Techniques, and Tools (2nd Edition)
A Java processor architecture for embedded real-time systems
Journal of Systems Architecture: the EUROMICRO Journal
Context-free language processing in time n3
SWAT '66 Proceedings of the 7th Annual Symposium on Switching and Automata Theory (swat 1966)
Efficient reconfigurable embedded parsers
Computer Languages, Systems and Structures
Parallel Parsing Algorithms and VLSI Implementations for Syntactic Pattern Recognition
IEEE Transactions on Pattern Analysis and Machine Intelligence
An efficient hardware implementation for AI applications
SETN'06 Proceedings of the 4th Helenic conference on Advances in Artificial Intelligence
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Attribute grammars (AG) allow the addition of context-sensitive properties into context free grammars, augmenting their expressional capabilities by using syntactic and semantic notations, making them in this way a really useful tool for a considerable number of applications. AGs have extensively been utilized in applications such as artificial intelligence, structural pattern recognition, compiler construction and even text editing. Obviously, the performance of an attribute evaluation system resides in the efficiency of the syntactic and semantic subsystems. In this paper, a hardware architecture for an attribute evaluation system is presented, which is based on an efficient combinatorial implementation of Earley's parallel parsing algorithm for the syntax part of the attribute grammar. The semantic part is managed by a special purpose module that traverses the parse tree and evaluates the attributes based on a proposed stack-based approach. The entire system is described in Verilog HDL (hardware design language), in a template form that given the specification of an arbitrary attribute grammar, the HDL synthesizable source code of the system is produced on the fly by a proposed automated tool. The generated code has been simulated for validation, synthesized and tested on an Xilinx FPGA (field programmable gate arrays) board for various AGs. Our method increases the performance up to three orders of magnitude compared to previous approaches, depending on the implementation, the size of the grammar and the input string length. This makes it particularly appealing for applications where attribute evaluation is a crucial aspect, like in real-time and embedded systems. Specifically, a natural language interface is presented, based on a question-answering application from the area of airline flights.