An efficient hardware implementation for AI applications

  • Authors:

  • Alexandros Dimopoulos;Christos Pavlatos;Ioannis Panagopoulos;George Papakonstantinou

  • Affiliations:

  • Dept. of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece;Dept. of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece;Dept. of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece;Dept. of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece

  • Venue:
  • SETN'06 Proceedings of the 4th Helenic conference on Advances in Artificial Intelligence
  • Year:
  • 2006

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Abstract

A hardware architecture is presented, which accelerates the per- formance of intelligent applications that are based on logic programming. The logic programs are mapped on hardware and more precisely on FPGAs (Field Programmable Gate Array). Since logic programs may easily be transformed into an equivalent Attribute Grammar (AG), the underlying model of implementing an embedded system for the aforementioned applications can be that of an AG evaluator. Previous attempts to the same problem were based on the use of two separate components. An FPGA was used for mapping the inference engine and a conventional RISC microprocessor for mapping the unification mechanism and user defined additional semantics. In this paper a new architecture is presented, in order to drastically reduce the number of the required processing elements by a factor of n (length of input string). This fact and the fact of using, for the inference engine, an extension of the most efficient parsing algorithm, allowed us to use only one component i.e. a single FPGA board, eliminating the need for an additional external RISC microprocessor, since we have embedded two “PicoBlaze” Soft Processors into the FPGA. The proposed architecture is suitable for embedded system applications where low cost, portability and low power consumption is of crucial importance. Our approach was tested with numerous examples in order to establish the performance improvement over previous attempts.