An attribute grammar interpreter as a knowledge engineering tool
Angewandte Informatik
Rule-based systems and pattern recognition
Pattern Recognition Letters
Detection of the P and T waves in an ECG
Computers and Biomedical Research
Syntactic Pattern Recognition of the ECG
IEEE Transactions on Pattern Analysis and Machine Intelligence
Parallel Recognition and Parsing on the Hypercube
IEEE Transactions on Computers
A grammatical view of logic programming
A grammatical view of logic programming
Attribute grammar paradigms—a high-level methodology in language implementation
ACM Computing Surveys (CSUR)
A parallel parsing algorithm for arbitrary context-free grammars
Information Processing Letters
Griebach normal form transformation revisited
Information and Computation
A syntactic approach applied to materials degradation
Pattern Recognition Letters
An Improved Context-Free Recognizer
ACM Transactions on Programming Languages and Systems (TOPLAS)
An efficient context-free parsing algorithm
Communications of the ACM
Introduction to Formal Language Theory
Introduction to Formal Language Theory
The theory of parsing, translation, and compiling
The theory of parsing, translation, and compiling
An FPGA-Based Coprocessor for the Parsing of Context-Free Grammars
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
General context-free language recognition.
General context-free language recognition.
An Embedded Microprocessor for Intelligent Control
Journal of Intelligent and Robotic Systems
Pattern Recognition Letters
A bibliographical study of grammatical inference
Pattern Recognition
Parallel Parsing Algorithms and VLSI Implementations for Syntactic Pattern Recognition
IEEE Transactions on Pattern Analysis and Machine Intelligence
A Formal Method for Rapid SoC Prototyping
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
A platform for the automatic generation of attribute evaluation hardware systems
Computer Languages, Systems and Structures
A direct method for optimal VLSI realization of deeply nested n-D loop problems
Microprocessors & Microsystems
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This paper presents a highly efficient architecture for the hardware implementation of context-free grammar (CFG) parsers. Its efficiency stems from an innovative combinatorial circuit that implements the fundamental operation of Earley's parsing algorithm in time complexity O(log"2|G|), where |G| is the size of the CFG. Using this hardware architecture in a template form, we have developed an automated synthesis tool that, given the specification of an arbitrary CFG, generates the HDL (Hardware Design Language) synthesizable source code of the hardware parser for the given grammar. The generated source has been simulated for validation, synthesized and tested on a Xilinx FPGA (Field Programmable Gate Array) board. Our method increases the performance by a factor of one to two orders of magnitude, compared to previous hardware implementations, depending on the size of the grammar and the input string length. The speedup, compared to the pure software implementation, varies from two orders of magnitude for toy-scale grammars to six orders of magnitude for large real life grammars. This makes it particularly appealing for applications where (syntactic) pattern recognition response is a crucial aspect.