Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Modern compiler implementation in Java
Modern compiler implementation in Java
Specialized Hardware for Deep Network Packet Filtering
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
An FPGA-Based Coprocessor for the Parsing of Context-Free Grammars
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Assisting Network Intrusion Detection with Reconfigurable Hardware
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A Parallel Parsing VLSI Architecture for Arbitrary Context Free Grammars
ICPADS '98 Proceedings of the 1998 International Conference on Parallel and Distributed Systems
Implementation of a Content-Scanning Module for an Internet Firewall
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A Methodology for Synthesis of Efficient Intrusion Detection Systems on FPGAs
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Snort - Lightweight Intrusion Detection for Networks
LISA '99 Proceedings of the 13th USENIX conference on System administration
Fast Regular Expression Matching Using FPGAs
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A Reconfigurable Architecture for Multi-Gigabit Speed Content-Based Routing
HOTI '06 Proceedings of the 14th IEEE Symposium on High-Performance Interconnects
Reconfigurable context-free grammar based data processing hardware with error recovery
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A 1 cycle-per-byte XML parsing accelerator
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Memory-side acceleration for XML parsing
NPC'11 Proceedings of the 8th IFIP international conference on Network and parallel computing
Improving the performance of message parsers for embedded systems
Proceedings of the 28th Annual ACM Symposium on Applied Computing
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This article presents a dense logic design for matching multiple regular expressions with a field programmable gate array (FPGA) at 10+ Gbps. It leverages on the design techniques that enforce the shortest critical path on most FPGA architectures while optimizing the circuit size. The architecture is capable of supporting a maximum throughput of 12.90 Gbps on a Xilinx Virtex 4 LX200 and its performance is linearly scalable with size. Additionally, this article presents techniques for parsing data streams to provide semantic information for patterns found within a data stream. We illustrate how a content-based router can be implemented with our parsing techniques using an XML parser as an example. The content-based router presented was designed, implemented, and tested in a Xilinx Virtex XCV2000E FPGA on the FPX platform. It is capable of processing 32-bits of data per clock cycle and runs at 100 MHz. This allows the system to process and route XML messages at 3.2 Gbps.