Synthesis and array processor realization of a 2-D IIR beam filter for wireless applications

Authors:
Rimesh M. Joshi;Arjuna Madanayake;Jithra Adikari;Len T. Bruton
Affiliations:
Department of Electrical and Computer Engineering, University of Akron, Akron, OH;Department of Electrical and Computer Engineering, University of Akron, Akron, OH;Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada;Department of Electrical and Computer Engineering, University of Calgary, Calgary, AB, Canada
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2012

Citing 12
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Electronically scanned RF-to-bits beam aperture arrays using 2-D IIR spatially bandpass digital filters

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Abstract

A broadband digital beamforming algorithm is proposed for directional filtering of temporally-broadband bandpass space-time plane-waves at radio frequencies (RFs). The enhancement of desired waves, as well as rejection of undesired interfering plane-waves, is simulated. A systolic-and wavefront-array architecture is proposed for the real-time implementation of second-order spatially-bandpass (SBP) 2-D infinite impulse response (IIR) beam filters having potential applications in broadband beamforming of temporally down-converted RF signals. The higher speed of operation and potentially reduced power consumption of the asynchronous architecture of wavefront-array processors (WAPs) in comparison to the conventional synchronous hardware has emerging applications in radio-astronomy, radar, navigation, space science, cognitive radio, and wireless communications. Further, the bit error rate (BER) performance improvement along with the reduced computational complexity of the 2-D IIR SBP frequency-planar digital filter over digital phased array feed (PAF) beamformer is provided. A nominal BER versus signal-to-interference ratio (SIR) gain of 10-16 dB compared to case where beamforming is not applied, and a gain of 2-3 dB at approximately half the number of parallel multipliers to digital PAF, are observed. The results of application-specific integrated circuit (ASIC) synthesis of the digital filter designs are also presented.