Synthesis and array processor realization of a 2-D IIR beam filter for wireless applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 35.68 |
Proposes novel systolic architectures for the real-time computation of the DFT and the DCT. The proposed architectures are suitable for implementation in the VLSI form. Extension of the proposed architectures for the real-time computation of the 2D version of these transforms is also given