Analysis of Graphs by Connectivity Considerations
Journal of the ACM (JACM)
Parallelism exposure and exploitation in programs
Parallelism exposure and exploitation in programs
A multiprocessor for simulation applications.
A multiprocessor for simulation applications.
Program Suitability for Parallel Processing
IEEE Transactions on Computers
Detection and Parallel Execution of Independent Instructions
IEEE Transactions on Computers
The Organization and Use of Parallel Memories
IEEE Transactions on Computers
Validity of the single processor approach to achieving large scale computing capabilities
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
Observations on high-performance machines
AFIPS '67 (Fall) Proceedings of the November 14-16, 1967, fall joint computer conference
A survey of techniques for recognizing parallel processable streams in computer programs
AFIPS '69 (Fall) Proceedings of the November 18-20, 1969, fall joint computer conference
An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors
IEEE Transactions on Computers
The Burroughs Scientific Processor (BSP)
IEEE Transactions on Computers
The Parallel Evaluation of Arithmetic Expressions Without Division
IEEE Transactions on Computers
Time and Parallel Processor Bounds for Linear Recurrence Systems
IEEE Transactions on Computers
High-Speed Multiprocessors and Compilation Techniques
IEEE Transactions on Computers
An Expression Model for Extraction and Evaluation of Parallelism in Control Structures
IEEE Transactions on Computers
Wavefront Array Processor: Language, Architecture, and Applications
IEEE Transactions on Computers
On the Analysis and Synthesis of VLSI Algorithms
IEEE Transactions on Computers
Measuring the Parallelism Available for Very Long Instruction Word Architectures
IEEE Transactions on Computers
Compilation Techniques for Recognition of Parallel Processable Tasks in Arithmetic Expressions
IEEE Transactions on Computers
Multiple Microprocessors with Common Main and Control Memories
IEEE Transactions on Computers
The Future of Parallel Processing
IEEE Transactions on Computers
Supercomputers for ordinary users
AFIPS '72 (Fall, part I) Proceedings of the December 5-7, 1972, fall joint computer conference, part I
An overview of the Texas reconfigurable array computer
AFIPS '80 Proceedings of the May 19-22, 1980, national computer conference
IJCAI'87 Proceedings of the 10th international joint conference on Artificial intelligence - Volume 1
Representation of Concurrency with Ordering Matrices
IEEE Transactions on Computers
Kremlin: rethinking and rebooting gprof for the multicore age
Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
Automatic introduction of mobility for standard-based frameworks
OTM'05 Proceedings of the 2005 Confederated international conference on On the Move to Meaningful Internet Systems - Volume >Part I
| Hi-index | 15.02 |
This paper is concerned with the problem of analyzing ordinary Fortran-like programs to determine how many of their operations could be performed simultaneously. Algorithms are presented for handling arithmetic assignment statements, DO loops and IF statement trees. The height of the parse trees of arithmetic expressions is reduced by distribution of multiplication over addition as well as the use of associativity and commutativity. DO loops are analyzed in terms of their index sets and subscript forms. Some general underlying assumptions about machine organization are also given. In terms of several measures which are defined, the results of experimental analyses are presented. About 20 Fortran IV programs consisting of nearly 1000 source cards were analyzed. Evidence is given that for very simple Fortran programs 16 processors could be effectively used operating simultaneously in a parallel or pipeline fashion. Thus, for medium or large size Fortran programs, machines consisting of multiples of a basic 16 processor unit could be used.