A parallel architecture for Kalman filter measurement update and parameter estimation
Automatica (Journal of IFAC)
Efficient Algorithms for Shortest Paths in Sparse Networks
Journal of the ACM (JACM)
Area-Efficient VLSI Computation
Area-Efficient VLSI Computation
Wavefront Array Processor: Language, Architecture, and Applications
IEEE Transactions on Computers
Computer
Optimizing synchronous systems
SFCS '81 Proceedings of the 22nd Annual Symposium on Foundations of Computer Science
Operation scheduling in reconfigurable, multifunction pipelines
ACM SIGMICRO Newsletter
A Family of New Efficient Arrays for Matrix Multiplication
IEEE Transactions on Computers
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In this paper, we take a hard look at scheduling considerations in computing arrays. A simple sufficient condition is developed for determining whether a computing array can be pipelined. If the array cannot be pipelined in the form given, the condition also indicates the direction in which to proceed to make it pipelineable. The overall framework and methodology take a good part of the load off the logical architect of the array, and make the translation from the logical to the physical architecture a mechanical process.