High performance programmable FPGA overlay for digital signal processing

Authors:
Séamas McGettrick;Kunjan Patel;Chris Bleakley
Affiliations:
UCD Complex and Adaptive Systems Laboratory, UCD School of Computer Science and Informatics, University College Dublin, Dublin, Ireland;UCD Complex and Adaptive Systems Laboratory, UCD School of Computer Science and Informatics, University College Dublin, Dublin, Ireland;UCD Complex and Adaptive Systems Laboratory, UCD School of Computer Science and Informatics, University College Dublin, Dublin, Ireland
Venue:
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Year:
2011

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Abstract

In this paper we investigate the use of a programmable overlay to increase the performance of variable DSP workloads executing on FPGAs. The overlay approach reduces reconfiguration time and provides fast processing. The overlay was implemented on a Virtex-5 110Lx FPGA and its performance was compared with that of a conventional GPP, DSP processor and custom FPGA implementation. It is found that both FPGA based architectures outperform the GPP and DSP processor implementations. Taking into account reconfiguration the programmable overlay was found to outperform the custom FPGA implementation for small and medium data sets. On a 255 FIR filter it was shown that the programmable overlay performed better than the custom hardware on all data sets below 40 million entries.