Digital image processing
Computer
Synthesis of an Optimal Family of Matrix Multiplication Algorithms on Linear Arrays
IEEE Transactions on Computers
Optimal Graph Algorithms on a Fixed-Size Linear Array
IEEE Transactions on Computers
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Mapping Homogeneous Graphs on Linear Arrays
IEEE Transactions on Computers
Modular Matrix Multiplication on a Linear Array
IEEE Transactions on Computers
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Many signal and image processing applications impose a severe demand on the I/O bandwidth and computation power of general-purpose computers. The "systolic" concept offers guidelines in building cost-effective systems that balance I/O with computation. The resulting simplicity and regularity of such systems leads to modular designs suitable for VLSI implementation. We describe here a linear systolic array capable of evaluating a large class of inner-product functions used in signal and image processing. These include matrix multiplication, multidimensional convolutions using fixed or time-varying kernels, as well as various nonlinear functions of vectors. The system organization of a working prototype is also described.