Configuration of VLSI Arrays in the Presence of Defects
Journal of the ACM (JACM)
Systolic Processing and an Implementation for Signal and Image Processing
IEEE Transactions on Computers
Modular Matrix Multiplication on a Linear Array
IEEE Transactions on Computers
Computer
Wafer-scale integration of systolic arrays
SFCS '82 Proceedings of the 23rd Annual Symposium on Foundations of Computer Science
Synthesizing Linear Array Algorithms from Nested FOR Loop Algorithms
IEEE Transactions on Computers
On Systolic Contractions of Program Graphs
IEEE Transactions on Computers
On Synthesizing Optimal Family of Linear Systolic Arrays for Matrix Multiplication
IEEE Transactions on Computers
Some New Designs of 2-D Array for Matrix Multiplication and Transitive Closure
IEEE Transactions on Parallel and Distributed Systems
A Modular Systolic Linearization of the Warshall-Floyd Algorithm
IEEE Transactions on Parallel and Distributed Systems
An Approach to Designing Modular Extensible Linear Arrays for Regular Algorithms
IEEE Transactions on Computers
A Family of New Efficient Arrays for Matrix Multiplication
IEEE Transactions on Computers
Mapping Nested Loop Algorithms into Multidimensional Systolic Arrays
IEEE Transactions on Parallel and Distributed Systems
Mapping dynamic programming onto modular linear systolic arrays
Distributed Computing
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Synthesis of a family of matrix multiplication algorithms on a linear array is described. All these algorithms are optimal in their area and time requirements. An important feature of the family of algorithms is that they are modularly extensible, that is, larger problem sizes can be handled by cascading smaller arrays consisting of processors having a fixed amount of local storage. These algorithms exhibit a tradeoff between the number of processors required and the local storage within a processor. In particular, as the local storage increases the number of processors required to multiply the two matrices decrease.