Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
IEEE Transactions on Computers
Synthesis of an Optimal Family of Matrix Multiplication Algorithms on Linear Arrays
IEEE Transactions on Computers
Regular interactive algorithms and their implementations on processor arrays
Regular interactive algorithms and their implementations on processor arrays
VLSI array processors
Optimal Systolic Design for the Transitive Closure and the Shortest Path Problems
IEEE Transactions on Computers
Complexity of Matrix Product on a Class of Orthogonally Connected Systolic Arrays
IEEE Transactions on Computers
A Family of New Efficient Arrays for Matrix Multiplication
IEEE Transactions on Computers
Automatic synthesis of systolic arrays from uniform recurrent equations
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Design of Efficient Regular Arrays for Matrix Multiplication by Two-Step Regularization
IEEE Transactions on Parallel and Distributed Systems
A Family of Efficient Regular Arrays for Algebraic Path Problem
IEEE Transactions on Computers
Design of Space-Optimal Regular Arrays for Algorithms with Linear Schedules
IEEE Transactions on Computers
The Optimal Architecture Design of Two-Dimension Matrix Multiplication Jumping Systolic Array
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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In this paper, we present some new regular iterative algorithms for matrix multiplication and transitive closure. With these algorithms, by spacetime mapping the 2-D arrays with $2N - 1$ and $\lceil (3N - 1)/2\rceil$ execution times for matrix multiplication can be obtained. Meanwhile, we can derive a 2-D array with $4N - 2$ execution time for transitive closure based on the sequential Warshall-Floyd algorithm. All these new 2-D arrays for matrix multiplication and transitive closure have the advantages of faster and more regular than other previous designs.Index Terms驴Algorithm mapping, matrix multiplication, mesh array, systolic array, spherical array, transitive closure, VLSI architecture.