Graphs and algorithms
Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
IEEE Transactions on Computers
Regular interactive algorithms and their implementations on processor arrays
Regular interactive algorithms and their implementations on processor arrays
VLSI array processors
Journal of the ACM (JACM)
The Organization of Computations for Uniform Recurrence Equations
Journal of the ACM (JACM)
Communications of the ACM
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
Automatic synthesis of systolic arrays from uniform recurrent equations
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Computer
Synthesizing Linear Array Algorithms from Nested FOR Loop Algorithms
IEEE Transactions on Computers
Multi-Input fuzzy inference engine on a systolic array
IEA/AIE '88 Proceedings of the 1st international conference on Industrial and engineering applications of artificial intelligence and expert systems - Volume 2
A Note on the Linear Transformation Method for Systolic Array Design
IEEE Transactions on Computers
An Optimal Systolic Array for the Algebraic Path Problem
IEEE Transactions on Computers
Design of Optimal Systolic Algorithms for the Transitive Closure Problem
IEEE Transactions on Computers
Some New Designs of 2-D Array for Matrix Multiplication and Transitive Closure
IEEE Transactions on Parallel and Distributed Systems
Optimal Synthesis of Algorithm-Specific Lower-Dimensional Processor Arrays
IEEE Transactions on Parallel and Distributed Systems
A Modular Systolic Linearization of the Warshall-Floyd Algorithm
IEEE Transactions on Parallel and Distributed Systems
Systolic VLSI array for fuzzy logic in expart sytems
CSC '88 Proceedings of the 1988 ACM sixteenth annual conference on Computer science
A Space-Time Representation Method of Iterative Algorithms for the Design of Processor Arrays
Journal of VLSI Signal Processing Systems
IEEE Transactions on Computers
A Family of Efficient Regular Arrays for Algebraic Path Problem
IEEE Transactions on Computers
Design of Space-Optimal Regular Arrays for Algorithms with Linear Schedules
IEEE Transactions on Computers
Mapping Nested Loop Algorithms into Multidimensional Systolic Arrays
IEEE Transactions on Parallel and Distributed Systems
Uniform Approach for Solving some Classical Problems on a Linear Array
IEEE Transactions on Parallel and Distributed Systems
A Processor-Time-Minimal Systolic Array for Transitive Closure
IEEE Transactions on Parallel and Distributed Systems
On Time Mapping of Uniform Dependence Algorithms into Lower Dimensional Processor Arrays
IEEE Transactions on Parallel and Distributed Systems
The Algebraic Path Problem Revisited
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
Observations on Parallel Computation of Transitive and Max-Closure Problems
Proceedings of the 9th European PVM/MPI Users' Group Meeting on Recent Advances in Parallel Virtual Machine and Message Passing Interface
An introduction to processor-time-optimal systolic arrays
Highly parallel computaions
Computing transitive closure on systolic arrays of fixed size
Distributed Computing
Towards systolizing compilation
Distributed Computing
Work-efficient BSR-based parallel algorithms for some fundamental problems in graph theory
The Journal of Supercomputing
The Journal of Supercomputing
Parallel FPGA-based all-pairs shortest-paths in a directed graph
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Computing transitive closure problem on linear systolic array
NAA'04 Proceedings of the Third international conference on Numerical Analysis and its Applications
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Due to VLSI technological progress, algorithm- oriented array architectures, such as systolic arrays, appear to be very effective, feasible, and economic. This paper discusses how to design systolic arrays for the transitive closure and the shortest path problems. We shall focus on the Warshall algorithm for the transitive closure problem and the Floyd algorithm for the shortest path problem. These two algorithms share exactly the same structural formulation; therefore, they lead to the same systolic array design. In this paper, we first present a general method for mapping algorithms to systolic arrays. Using this methodology, two new systolic designs for the Warshall-Floyd algorithm will be derived. The first one is a spiral array, which is easy to derive and can be further simplified to a hexagonal array. The other is an orthogonal systolic array which is optimal in terms of pipelining rate, block pipelining rate, and the number of input/output connections.