Regular interactive algorithms and their implementations on processor arrays
Regular interactive algorithms and their implementations on processor arrays
VLSI array processors
Computer benchmarking: paths and pitfalls
IEEE Spectrum
Optimal Systolic Design for the Transitive Closure and the Shortest Path Problems
IEEE Transactions on Computers
Solving problems on concurrent processors
Solving problems on concurrent processors
On-line scheme for computing rotation factors
Journal of Parallel and Distributed Computing - Parallelism in Computer Arithmetic
Systematic design approaches for algorithmically specified systolic arrays
Computer architecture
SIGARCH Third Conference on Hypercube Concurrent Computers and Applications
Matrix computations on mesh arrays
Matrix computations on mesh arrays
Redundant and On-Line CORDIC: Application to Matrix Triangularization and SVD
IEEE Transactions on Computers
Comparing design methods based on index-dependencies and on data-dependencies
Systolic array processors
The Organization of Computations for Uniform Recurrence Equations
Journal of the ACM (JACM)
Advanced Algorithms and Architectures for Signal Processing III
Advanced Algorithms and Architectures for Signal Processing III
Advanced Algorithms and Architectures for Signal Processing
Advanced Algorithms and Architectures for Signal Processing
On Synthesizing Systolic Arrays from Recurrence Equations with Linear Dependencies
Proceedings of the Sixth Conference on Foundations of Software Technology and Theoretical Computer Science
Automatic synthesis of systolic arrays from uniform recurrent equations
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Optimization of the background memory utilization by partitioning
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Designing a Scalable Processor Array for Recurrent Computations
IEEE Transactions on Parallel and Distributed Systems
A Space-Time Representation Method of Iterative Algorithms for the Design of Processor Arrays
Journal of VLSI Signal Processing Systems
An Efficient Algorithm-Based Fault Tolerance Design Using the Weighted Data-Check Relationship
IEEE Transactions on Computers
A Fast Algorithm for Matrix Multiplication and Its Efficient Realization on Systolic Arrays
Cybernetics and Systems Analysis
Scheduling in Co-Partitioned Array Architectures
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Encyclopedia of Computer Science
Qos Enhancement in Wireless VoIP Networks Using Interactive Multiple Model Based Kalman Filter
Wireless Personal Communications: An International Journal
Hi-index | 4.10 |
Systolic-type arrays use both the fine-grain parallelism and the regularity of matrix computations effectively. The multimesh graph method for deriving these arrays is systematic, flexible, and easy to use.