Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
IEEE Transactions on Computers
VLSI array processors
Optimal Systolic Design for the Transitive Closure and the Shortest Path Problems
IEEE Transactions on Computers
The systematic design of systolic arrays
Centre National de Recherche Scientifique on Automata networks in computer science: theory and applications
Synthesizing Linear Array Algorithms from Nested FOR Loop Algorithms
IEEE Transactions on Computers
Systematic design approaches for algorithmically specified systolic arrays
Computer architecture
Minimum Distance: A Method for Partitioning Recurrences for Multiprocessors
IEEE Transactions on Computers
The Organization of Computations for Uniform Recurrence Equations
Journal of the ACM (JACM)
The parallel execution of DO loops
Communications of the ACM
Parallel Programming and Compilers
Parallel Programming and Compilers
Structure of Computers and Computations
Structure of Computers and Computations
Mapping Nested Loop Algorithms into Multidimensional Systolic Arrays
IEEE Transactions on Parallel and Distributed Systems
A Loop Transformation Theory and an Algorithm to Maximize Parallelism
IEEE Transactions on Parallel and Distributed Systems
A Processor-Time-Minimal Systolic Array for Transitive Closure
IEEE Transactions on Parallel and Distributed Systems
On Loop Transformations for Generalized Cycle Shrinking
IEEE Transactions on Parallel and Distributed Systems
Compiling for Distributed Memory Architectures
IEEE Transactions on Parallel and Distributed Systems
Constructive Methods for Scheduling Uniform Loop Nests
IEEE Transactions on Parallel and Distributed Systems
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A novel Space-Time Representation (STR) of iterative algorithms for their systematic mapping ontoregular processor arrays is proposed. Timing information is introduced in the Dependence Graph (DG) by thedefinition and the construction of the Space-Time DG (STDG). Any variable instance of the loop body,independently of the number of the loop indices, is characterized by an integer vector composed by itsindices, as space part, and an additional time index, representing its execution time according to apreliminary timing. The main advantage of the STR is that the need for the uniformization of the algorithmis avoided. Moreover, it is proven that in the STDG dependence vectors having opposite directions do notexist and therefore a linear mapping of the STDG onto the desired processor array can always be derived. Efficient 2D and 1D regular architectures are produced by applying the STR to the original description ofthe Warshall-Floyd algorithm for the Algebraic Path Problem.