Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
IEEE Transactions on Computers
Regular interactive algorithms and their implementations on processor arrays
Regular interactive algorithms and their implementations on processor arrays
VLSI array processors
Optimal Systolic Design for the Transitive Closure and the Shortest Path Problems
IEEE Transactions on Computers
Synthesizing Linear Array Algorithms from Nested FOR Loop Algorithms
IEEE Transactions on Computers
Quasi-regular arrays: definition and design methodology
Systolic array processors
Time Optimal Linear Schedules for Algorithms with Uniform Dependencies
IEEE Transactions on Computers
An Optimal Systolic Array for the Algebraic Path Problem
IEEE Transactions on Computers
Calculus of space-optimal mappings of systolic algorithms on processor arrays
Journal of VLSI Signal Processing Systems - Special issue: application specific array processors
Design of Efficient Regular Arrays for Matrix Multiplication by Two-Step Regularization
IEEE Transactions on Parallel and Distributed Systems
Some New Designs of 2-D Array for Matrix Multiplication and Transitive Closure
IEEE Transactions on Parallel and Distributed Systems
A Family of Efficient Regular Arrays for Algebraic Path Problem
IEEE Transactions on Computers
A Processor-Time-Minimal Systolic Array for Cubical Mesh Algorithms
IEEE Transactions on Parallel and Distributed Systems
A Processor-Time-Minimal Systolic Array for Transitive Closure
IEEE Transactions on Parallel and Distributed Systems
Space-Optimal Linear Processor Allocation for Systolic Arrays Synthesis
IPPS '92 Proceedings of the 6th International Parallel Processing Symposium
Automatic synthesis of systolic arrays from uniform recurrent equations
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Combinatorial Algorithms: Theory and Practice
Combinatorial Algorithms: Theory and Practice
Mapping rectangular mesh algorithms onto asymptotically space-optimal arrays
Journal of Parallel and Distributed Computing
Complexity of matrix product on modular linear systolic arrays for algorithms with affine schedules
Journal of Parallel and Distributed Computing
Mapping matrix multiplication algorithm onto fault-tolerant systolic array
Computers & Mathematics with Applications
| Hi-index | 14.98 |
The problem of designing space-optimal 2D regular N脳N脳N cubical mesh algorithms with linear schedule ai+bj+ck, 1 驴a驴b驴c, and N=nc, is studied. Three novel nonlinear processor allocation methods, each of which works by combining a partitioning technique (gcd-partition) with different nonlinear processor allocation procedures (traces), are proposed to handle different cases. In cases where a+b驴c, which are dealt with by the first processor allocation method, space-optimal designs can always be obtained in which the number of processing elements is equal to ${N^2\over c}$. For other cases where a+b c and either a=b and b=c, two other optimal processor allocation methods are proposed. Besides, the closed form expressions for the optimal number of processing elements are derived for these cases.