Communicating sequential processes
Communicating sequential processes
Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
IEEE Transactions on Computers
Regular interactive algorithms and their implementations on processor arrays
Regular interactive algorithms and their implementations on processor arrays
Optimal Systolic Design for the Transitive Closure and the Shortest Path Problems
IEEE Transactions on Computers
The derivation of systolic implementations
Acta Informatica
Mapping a single-assignment language onto the Warp systolic array
Proc. of a conference on Functional programming languages and computer architecture
The warp computer: Architecture, implementation, and performance
IEEE Transactions on Computers
Transputer reference manual
Synthesizing Linear Array Algorithms from Nested FOR Loop Algorithms
IEEE Transactions on Computers
Code generation for a systolic computer
Software—Practice & Experience
A mechanically derived systolic implementation of pyramid initialization
Proceedings of the Mathematical Sciences Institute workshop on Hardware specification, verification and synthesis: mathematical aspects
Quasi-regular arrays: definition and design methodology
Systolic array processors
Single-Assignment Semantics for Imperative Programs
PARLE '89 Proceedings of the Parallel Architectures and Languages Europe, Volume II: Parallel Languages
Automatic synthesis of systolic arrays from uniform recurrent equations
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
The mechanically certified derivation of concurrency and its application to systolic design
The mechanically certified derivation of concurrency and its application to systolic design
Occam Programming Manual
From functional equations to Occam programs: systolizing compilation
PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques
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A scheme for the compilation of imperative or functional programs into systolic programs is demonstrated on matrix composition/decomposition and Gauss-Jordan elimination. Using this scheme, programs for the processor network Warp and for several transputer networks have been generated.