Synthesis of an Optimal Family of Matrix Multiplication Algorithms on Linear Arrays
IEEE Transactions on Computers
On Mapping Cube Graphs onto VLSI Arrays
Proceedings of the Fourth Conference on Foundations of Software Technology and Theoretical Computer Science
On mapping algorithms onto processor arrays
On mapping algorithms onto processor arrays
| Hi-index | 14.98 |
A variant of the mapping problem, namely, systolic contractions of program graphs, is considered. The notion of time links is introduced to mechanize the contraction process; the timing of information flow between processors is modeled in terms of fundamental loop and path equations of delays and is optimized using linear programming. While the results apply primarily to systolic contractions, they can be extended to other types of graph contractions by relaxing the time constraints imposed by delay equations. Such contractions can, in principle, lead to faster execution of program graphics, since they may do away with the delays imposed on the links between the processors by systolic contractions. Clearly, storage is traded for time since extra storage may be necessary to hold some operands temporarily until a processor acquires all of its operands for a computation.